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LNK353/354 linkswitch-hf family enhanced, energy ef?cient, low power off-line switcher ic figure 1. typical standby application. product highlights features optimized for lowest system cost ? fully integrated auto-restart for short-circuit and open loop protection ? self-biased supply C saves transformer auxiliary winding and associated bias supply components ? tight tolerances and negligible temperature variation on key parameters eases design and lowers cost ? high maximum switching frequency allows very low ?ux density transformer designs, practically eliminating audible noise ? frequency jittering greatly reduces emi ? packages with large creepage to high voltage pin ? lowest component count switcher solution much better performance over linear/rcc ? lower system cost than rcc, discrete pwm and other integrated solutions ? universal input range allows worldwide operation ? simple on/off control C no loop compensation needed ? no bias winding C simpler, lower cost transformer ? high frequency switching C smaller and lower cost transformer ? very low component count C higher reliability and single side printed circuit board ? high bandwidth provides fast turn on with no overshoot and excellent transient load response ? current limit operation rejects line frequency ripple ? built-in current limit and hysteretic thermal shutdown protection ecosmart ? C extremely energy ef?cient ? no-load consumption <300 mw without bias winding at 265 vac input ? meets california energy commission (cec), energy star, and eu requirements applications ? chargers for cell/cordless phones, pdas, digital cameras, mp3/portable audio devices, shavers etc. ? standby and auxiliary supplies description linkswitch-hf integrates a 700 v power mosfet, oscillator, simple on/off control scheme, a high voltage switched current ? table 1. notes: 1. typical continuous power in a non-ventilated enclosed adapter measured at 50 c ambient. 2. maximum practical continuous power in an open frame design with adequate heat sinking, measured at 50 c ambient. 3. packages: p: dip-8b, g: smd-8b. for lead-free package options, see part ordering information. 4. for designs without a y capacitor, the available power may be lower (see key applications considerations). source, frequency jittering, cycle-by-cycle current limit, and thermal shutdown circuitry onto a monolithic ic. the start-up and operating power are derived directly from the drain pin, eliminating the need for a bias winding and associated circuitry. the 200 khz maximum switching frequency allows very low ?ux transformer designs, practically eliminating audible noise with the simple on/off control scheme using standard varnished transformer construction. ef?cient operation at this high switching frequency is achieved due to the optimized switching characteristics and small capacitances of the integrated power mosfet. the fully integrated auto-restart circuit safely limits output power during fault conditions such as output short circuit or open loop, reducing component count and secondary feedback circuitry cost. the internal oscillator frequency is jittered to signi?cantly reduce both the quasi-peak and average emi, minimizing ?ltering cost. dc output wide range hv dc input pi-3855-022704 + + linkswitch-hf d s bp fb february 2005 output power table product (3) 230 vac 15% 85-265 vac adapter (1) open frame (2) adapter (1) open frame (2) LNK353 p or g 3 w 4 w 2.5 w (4) 3 w lnk354 p or g 3.5 w 5 w 3 w (4) 4.5 w
LNK353/354 f 2/05 2 pi-2367-021105 clock jitter oscilla to r 5.8 v 4.85 v source (s) s r q dc max byp ass (bp) fa ul t present + - v i limi t leading edge blanking thermal shutdown + - drain (d) regula to r 5.8 v byp ass pi n under-vol t age current limit comp ara to r feedback (fb) q 6.3 v reset aut o- rest art counter 1.65 v -v t clock figure 3. pin con?guration. pin functional description drain (d) pin: power mosfet drain connection. provides internal operating current for both start-up and steady-state operation. bypass (bp) pin: connection point for a 0.1 f external bypass capacitor for the internally generated 5.8 v supply. feedback (fb) pin: during normal operation, switching of the power mosfet is controlled by this pin. mosfet switching is terminated when a current greater than 49 a is delivered into this pin. source (s) pin: this pin is the power mosfet source connection. it is also the ground reference for the bypass and feedback pins. pi-3491-111903 fb d s bp s s s p package (dip-8b) g package (smd-8b) 8 5 7 1 4 2 3 figure 2. functional block diagram.
LNK353/354 f 2/05 3 pi-3857-022504 0 6.4 time ( s) 0 100 200 400 500 600 300 v drain 208 kh z 192 kh z linkswitch-hf functional description linkswitch-hf combines a high voltage power mosfet switch with a power supply controller in one device. unlike conventional pwm (pulse width modulator) controllers, linkswitch-hf uses a simple on/off control to regulate the output voltage. the linkswitch-hf controller consists of an oscillator, feedback (sense and logic) circuit, 5.8 v regulator, bypass pin under-voltage circuit, over-temperature protection, frequency jittering, current limit circuit, leading edge blanking and a 700 v power mosfet. the linkswitch-hf incorporates additional circuitry for auto-restart. oscillator the typical oscillator frequency is internally set to an average of 200 khz. two signals are generated from the oscillator: the maximum duty cycle signal (dc max ) and the clock signal that indicates the beginning of each cycle. the linkswitch-hf oscillator incorporates circuitry that introduces a small amount of frequency jitter, typically 16 khz peak-to-peak, to minimize emi emission. the modulation rate of the frequency jitter is set to 1.5 khz to optimize emi reduction for both average and quasi-peak emissions. the frequency jitter should be measured with the oscilloscope triggered at the falling edge of the drain waveform. the waveform in figure 4 illustrates the frequency jitter of the linkswitch-hf . feedback input circuit the feedback input circuit at the fb pin consists of a low impedance source follower output set at 1.65 v. when the current delivered into this pin exceeds 49 a, a low logic level (disable) is generated at the output of the feedback circuit. this output is sampled at the beginning of each cycle on the rising edge of the clock signal. if high, the power mosfet is turned on for that cycle (enabled), otherwise the power mosfet remains off (disabled). since the sampling is done only at the beginning of each cycle, subsequent changes in the fb pin voltage or current during the remainder of the cycle are ignored. 5.8 v regulator and 6.3 v shunt voltage clamp the 5.8 v regulator charges the bypass capacitor connected to the bypass pin to 5.8 v by drawing a current from the voltage on the drain, whenever the mosfet is off. the bypass pin is the internal supply voltage node for the linkswitch-hf . when the mosfet is on, the linkswitch-hf runs off of the energy stored in the bypass capacitor. extremely low power consumption of the internal circuitry allows the linkswitch-hf to operate continuously from the current drawn from the drain pin. a bypass capacitor value of 0.1 f is suf?cient for both high frequency decoupling and energy storage. in addition, there is a 6.3 v shunt regulator clamping the bypass pin at 6.3 v when current is provided to the bypass pin through an external resistor. this facilitates powering of linkswitch-hf externally through a bias winding to decrease the no-load consumption to less than 50 mw. bypass pin under-voltage the bypass pin under-voltage circuitry disables the power mosfet when the bypass pin voltage drops below 4.85 v. once the bypass pin voltage drops below 4.85 v, it must rise back to 5.8 v to enable (turn-on) the power mosfet. over-temperature protection the thermal shutdown circuitry senses the die temperature. the threshold is set at 142 c typical with a 75 c hysteresis. when the die temperature rises above this threshold (142 c) the power mosfet is disabled and remains disabled until the die temperature falls by 75 c, at which point it is re-enabled. current limit the current limit circuit senses the current in the power mosfet. when this current exceeds the internal threshold (i limit ), the power mosfet is turned off for the remainder of that cycle. the leading edge blanking circuit inhibits the current limit comparator for a short time (t leb ) after the power mosfet is turned on. this leading edge blanking time has been set so that current spikes caused by capacitance and recti?er reverse recovery time will not cause premature termination of the switching pulse. auto-restart in the event of a fault condition such as output overload, output short circuit, or an open loop condition, linkswitch-hf enters into auto-restart operation. an internal counter clocked by the oscillator gets reset every time the fb pin is pulled high. if the fb pin is not pulled high for 30 ms, the power mosfet switching is disabled for 650 ms. the auto-restart alternately enables and disables the switching of the power mosfet until the fault condition is removed. figure 4. frequency jitter.
LNK353/354 f 2/05 4 applications example a 2.4 w cc/cv charger adapter the circuit shown in figure 5 is a typical implementation of a 5.7 v, 400 ma, constant voltage, constant current (cv/cc) battery charger. the input bridge formed by diodes d1-d4, recti?es the ac input voltage. the recti?ed ac is then ?ltered by the bulk storage capacitors c1 and c2. resistor rf1 is a ?ameproof, fusible, wire wound type and functions as a fuse, inrush current limiter and, together with the ?lter formed by c1, c2 and l1, differential mode noise attenuator. this simple emi ?ltering, together with the frequency jittering of linkswitch-hf (u1), a small value y1 capacitor (cy1), and shield windings within t1, and a secondary-side rc snubber (r5, c5), allows the design to meet both conducted and radiated emi limits. the low value of cy1 is important to meet the requirement of low line frequency leakage current, in this case <10 a. the recti?ed and ?ltered input voltage is applied to the primary winding of t1. the other side of the transformer primary is driven by the integrated mosfet in u1. diode d5, c3, r1 and r3 form the primary clamp network. this limits the peak drain voltage due to leakage inductance. resistor r3 allows the use of a slow, low cost recti?er diode by limiting the reverse current through d5 when u1 turns on. the selection of a slow diode improves ef?ciency and conducted emi. output recti?cation is provided by schottky diode d6. the low forward voltage provides high ef?ciency across the operating range and the low esr capacitor c6 minimizes output voltage ripple. in constant voltage (cv) mode, the output voltage is set by the zener diode vr1 and the emitter-base voltage of pnp transistor q1. the v be of q1 divided by the value of r7 sets the bias current through vr1 (~2.7 ma). when the output voltage exceeds the threshold voltage determined by q1 and vr1, q1 is turned on and current ?ows through the led of u2. as the led current increases, the current fed into the feedback pin increases, disabling further switching cycles of u1. at very light loads, almost all switching cycles will be disabled, giving a low effective switching frequency and providing low no-load consumption. during load transients, r6 and r8 ensure that the ratings of q1 are not exceeded while r4 prevents c4 from being discharged. resistors r9 and r10 form the constant current (cc) sense circuit. above approximately 400 ma, the voltage across the sense resistor exceeds the optocoupler diode forward conduction voltage of approximately 1 v. the current through the led is therefore determined by the output current and cc control dominates over the cv feedback loop. cc control is maintained even under output short circuit conditions. d s fb bp rf1 8.2 ? 2.5 w 85-265 va c 5.7 v, 400 ma j3-2 rtn j3-1 j1 j2 r3 200 ? r5 68 ? r1 100 k ? r4 5.1 k ? r6 6.8 ? r9 200 ? r10 2.4 ? 1 w r8 390 ? u2a pc817d vr1 bzx79b5v1 5.1 v, 2% r7 220 ? u2b pc817d d1 1n4005 d2 1n4005 d5 1n4007gp d3 1n4005 d4 1n4005 d6 ss14 c6 330 f 16 v q1 mmst 3906 l1 1 mh cy1 100 pf c1 4.7 f 400 v c3 2.2 nf 400 v 5 3 4 5 9 8 t1 ee16 nc nc u1 lnk354p c2 4.7 f 400 v c4 100 nf c5 2.2 nf linkswitch-hf pi-3891-070204 figure 5. universal input, 5.7 v, 400 ma, constant voltage, constant current battery charger using linkswitch-hf.
LNK353/354 f 2/05 5 key application considerations linkswitch-hf design considerations output power table data sheet maximum output power table (table 1) represents the maximum practical continuous output power level that can be obtained under the following assumed conditions: 1. the minimum dc input voltage is 90 v or higher for 85 vac input, or 240 v or higher for 230 vac input or 115 vac with a voltage doubler. the value of the input capacitance should be large enough to meet these criteria for ac input designs. 2. secondary output of 5.5 v with a schottky recti?er diode. 3. assumed ef?ciency of 70%. 4. operating frequency of f osc(min) and i limit(min) . 5. voltage only output (no secondary side constant current circuit). 6. continuous mode operation (0.6 k p 1). 7. the part is board mounted with source pins soldered to a suf?cient area of copper to keep the source pin temperature at or below 100 c. 8. ambient temperature of 50 c for open frame designs and an internal enclosure temperature of 60 c for adapter designs. below a value of 1, k p is the ratio of ripple to peak primary current. above a value of 1, k p is the ratio of primary mosfet off time to the secondary diode conduction time. operating at a lower effective switching frequency can simplify meeting conducted and radiated emi limits, especially for designs where the safety y capacitor must be eliminated. by using a lower effective full load frequency, the calculated value of the primary inductance is higher than required for power delivery. however, the maximum power capability at this lower operating frequency will be lower than the values shown in table 1. audible noise the cycle skipping mode of operation used in linkswitch-hf can generate audio frequency components in the transformer. to limit this audible noise generation, the transformer should be designed such that the peak core ?ux density is below 1250 gauss (125 mt). following this guideline and using the standard transformer production technique of dip varnishing practically eliminates audible noise. higher ?ux densities are possible however, careful evaluation of the audible noise performance should be made using production transformer samples before approving the design. ceramic capacitors that use dielectrics such as z5u, when used in clamp circuits, may also generate audio noise. if this is the case, try replacing them with a capacitor having a different dielectric, for example a polyester ?lm type. linkswitch-hf layout considerations see figure 6 for a recommended circuit board layout for linkswitch-hf . single point grounding use a single point ground connection from the input ?lter capacitor to the area of copper connected to the source pins. bypass capacitor (c bp ) the bypass pin capacitor should be located as near as possible to the bypass and source pins. primary loop area the area of the primary loop that connects the input ?lter capacitor, transformer primary and linkswitch-hf together should be kept as small as possible. primary clamp circuit a clamp is used to limit peak voltage on the drain pin at turn off. this can be achieved by using an rcd clamp (as shown in figure 5) or a zener (~200 v) and diode clamp across the primary winding. in all cases, to minimize emi, care should be taken to minimize the circuit path from the clamp components to the transformer and linkswitch-hf . thermal considerations the copper area underneath the linkswitch-hf acts not only as a single point ground, but also as a heatsink. as this area is connected to the quiet source node, this area should be maximized for good heatsinking of linkswitch-hf . the same applies to the cathode of the output diode. y-capacitor the placement of the y-capacitor should be directly from the primary input ?lter capacitor positive terminal to the common/return terminal of the transformer secondary. such a placement will route high magnitude common mode surge currents away from the linkswitch-hf device. note that if an input (c, l, c) emi ?lter is used, then the inductor in the ?lter should be placed between the negative terminals of the input ?lter capacitors. optocoupler place the optocoupler physically close to the linkswitch-hf to minimize the primary side trace lengths. keep the high current, high voltage drain and clamp traces away from the optocoupler to prevent noise pick up. output diode for best performance, the area of the loop connecting the secondary winding, the output diode and the output ?lter capacitor should be minimized. in addition, suf?cient copper area should be provided at the anode and cathode terminals
LNK353/354 f 2/05 6 of the diode for heatsinking. a larger area is preferred at the quiet cathode terminal. a large anode area can increase high frequency radiated emi. quick design checklist as with any power supply design, all linkswitch-hf designs should be veri?ed on the bench to make sure that component speci?cations are not exceeded under worst-case conditions. the following minimum set of tests is strongly recommended: 1. maximum drain voltage C verify that v ds does not exceed 675 v at the highest input voltage and peak (overload) output power. 2. maximum drain current C at maximum ambient temperature, maximum input voltage and peak output (overload) power, verify drain current waveforms for any signs of transformer saturation and excessive leading edge current spikes at startup. repeat under steady state conditions and verify that figure 6. recommended printed circuit layout for linkswitch-hf in a flyback converter con?guration. the leading edge current spike event is below i limit(min) at the end of the t leb(min) . under all conditions, the maximum drain current should be below the speci?ed absolute maximum ratings. 3. thermal check C at speci?ed maximum output power, minimum input voltage and maximum ambient temperature, verify that the temperature speci?cations are not exceeded for linkswitch-hf , transformer, output diode, and output capacitors. enough thermal margin should be allowed for part-to-part variation of the r ds(on) of linkswitch-hf as speci?ed in the data sheet. under low line, maximum power, a maximum linkswitch-hf source pin temperature of 100 c is recommended to allow for these variations. design tools up-to-date information on design tools can be found at the power integrations website: www.powerint.com. + hv dc input pi-3890-102704 input filter capacitor c bp - dc out output filter capacitor y1- capacitor maximize hatched copper areas ( ) for optimum heatsinking to p view d s s b p f b s s linkswitch-hf + - opto- coupler pri sec t r a n s f o r m e r
LNK353/354 f 2/05 7 absolute maximum ratings (1,5) drain voltage .................................. ................ -0.3 v to 700 v peak drain current......................................400 ma (750 ma) (2) feedback voltage ................................................ -0.3 v to 9 v feedback current .................................................... 100 ma bypass voltage...................................................... -0.3 v to 9 v storage temperature .......................................... -65 c to 150 c operating junction temperature (3) ..................... -40 c to 150 c lead temperature (4) .......................................................... 260 c notes: 1. all voltages referenced to source, t a = 25 c. 2. the higher peak drain current is allowed while the drain voltage is less than 400 v. 3. normally limited by internal circuitry. 4. 1/16 in. from case for 5 seconds. 5. maximum ratings speci?ed may be applied, one at a time, without causing permanent damage to the product. exposure to absolute maximum rating conditions for extended periods of time may affect product reliability. thermal impedance thermal impedance: p or g package: ( ja ) ........................... 70 c/w (2) ; 60 c/w (3) ( jc ) (1) ............................................... 11 c/w notes: 1. measured on pin 2 (source) close to plastic interface. 2. soldered to 0.36 sq. in. (232 mm 2 ), 2 oz. (610 g/m 2 ) copper clad. 3. soldered to 1 sq. in. (645 mm 2 ), 2 oz. (610 g/m 2 ) copper clad. parameter symbol conditions source = 0 v; t j = -40 to 125 c see figure 7 (unless otherwise speci?ed) min typ max units control functions output frequency f osc t j = 25 c average 186 200 214 khz peak-peak jitter 16 maximum duty cycle dc max s2 open 60 63 % feedback pin turnoff threshold current i fb t j = 25 c 30 49 68 a feedback pin voltage v fb i fb = 49 a 1.54 1.65 1.76 v drain supply current i s1 v fb 2 v (mosfet not switching) see note a 200 275 a i s2 feedback open (mosfet switching) see notes a, b 280 365 a bypass pin charge current i ch1 v bp = 0 v, t j = 25 c see note c -5.5 -3.3 -1.8 ma i ch2 v bp = 4 v, t j = 25 c see note c -3.8 -2.1 -1.0 bypass pin voltage v bp 5.55 5.8 6.10 v bypass pin voltage hysteresis v bph 0.8 0.95 1.2 v
LNK353/354 f 2/05 8 parameter symbol conditions source = 0 v; t j = -40 to 125 c see figure 7 (unless otherwise speci?ed) min typ max units control functions (cont) bypass pin supply current i bpsc see note d 68 a circuit protection current limit i limit (see note e) di/dt = 90 ma/ s t j = 25 c LNK353 172 185 198 ma di/dt = 400 ma/ s t j = 25 c 215 245 274 di/dt = 115 ma/ s t j = 25 c lnk354 233 250 268 di/dt = 500 ma/ s t j = 25 c 264 300 336 minimum on time t on(min) LNK353 390 470 610 ns lnk354 280 360 500 leading edge blanking time t leb t j = 25 c see note f 170 215 ns thermal shutdown temperature t sd 135 142 150 c thermal shutdown hysteresis t shd see note g 75 c output on-state resistance r ds(on) LNK353 i d = 25 ma t j = 25 c 34 40 ? t j = 100 c 54 63 lnk354 i d = 25 ma t j = 25 c 24 28 t j = 100 c 38 45 off-state drain leakage current i dss v bp = 6.2 v, v fb 2 v, v ds = 560 v, t j = 125 c 50 a breakdown voltage bv dss v bp = 6.2 v, v fb 2 v, t j = 25 c 700 v rise time t r measured in a typical flyback converter application 50 ns fall time t f 50 ns
LNK353/354 f 2/05 9 parameter symbol conditions source = 0 v; t j = -40 to 125 c see figure 7 (unless otherwise speci?ed) min typ max units output (cont) drain supply voltage 50 v output enable delay t en see figure 9 10 s output disable setup time t dst 0.5 s auto-restart on-time t ar t j = 25 c see note h 31 ms auto-restart duty cycle dc ar 5 % notes: a. total current consumption is the sum of i s1 and i dss when feedback pin voltage is 2 v (mosfet not switching) and the sum of i s2 and i dss when feedback pin is shorted to source (mosfet switching). b since the output mosfet is switching, it is dif?cult to isolate the switching current from the supply current at the drain. an alternative is to measure the bypass pin current at 6 v. c. see typical performance characteristics section figure 14 for bypass pin start-up charging waveform. d. this current is only intended to supply an optional optocoupler connected between the bypass and feedback pins and not any other external circuitry. e. for current limit at other di/dt values, refer to figure 13. f. this parameter is guaranteed by design. g. this parameter is derived from characterization. h. auto-restart on time has the same temperature characteristics as the oscillator (inversely proportional to frequency).
LNK353/354 f 2/05 10 figure 7. linkswitch-hf general test circuit. pi-3490-060204 50 v 50 v d fb s s s s bp s1 470 k ? s2 0.1 f 470 ? 5 w pi-2048-033001 drain voltage hv 0 v 90% 10% 90% t 2 t 1 d = t 1 t 2 pi-3707-112503 fb t p t en dc max t p = 1 f osc v drain (internal signal) figure 8. linkswitch-hf duty cycle measurement. figure 9. linkswitch-hf output enable timing.
LNK353/354 f 2/05 11 200 300 350 400 250 0 0 4 2 8 6 1 0 1 2 1 4 1 6 1 8 2 0 drain v oltage (v ) drain current (ma) pi-3949-102004 50 150 100 25 c 100 c scaling factors: LNK353 0. 7 lnk354 1. 0 typical performance characteristics figure 14. bypass pin start-up waveform. 1.1 1.0 0.9 -50 -25 0 2 5 5 0 7 5 100 125 150 junction temperature ( c) breakdown voltage (normalized to 25 c) pi-2213-012301 6 5 4 3 2 1 0 0 0.2 0.4 0.6 0.8 1.0 time (ms) pi-2240-012301 bypass pin voltage (v) 7 figure 10. breakdown vs. temperature. figure 12. current limit vs. temperature at normalized di/dt. figure 13. current limit vs. di/dt. figure 15. output characteristics. figure 11. frequency vs. temperature. tbd temperature ( c) pi-3709-111203 current limit (normalized to 25 c) 1.0 1.2 1.4 0.8 0.6 0.4 0.2 0 -50 0 5 0 100 150 di/dt = 1 di/dt = 6 normalized di/dt 1.2 1.0 0.8 0.6 0.4 0.2 0 -50 -25 0 2 5 5 0 7 5 100 125 junction temperature ( c) pi-2680-012301 output frequency (normalized to 25 c) normalized di/dt pi-3892-061604 normalized current limit 1.0 1.2 1.4 0.8 0.6 0.4 0.2 0 1 2 3 4 5 LNK353 lnk354 LNK353 lnk354 normalized di/dt = 1 90 ma/ s 115 ma/ s normalized current limit = 1 185 ma 250 ma
LNK353/354 f 2/05 12 drain voltage (v) drain capacitance (pf) pi-3888-052104 0 100 200 300 400 500 600 1 10 100 1000 figure 16. c oss vs. drain voltage. typical performance characteristics (cont.) part ordering information linkswitch product family hf series number package identi?er g plastic surface mount dip p plastic dip lead finish blank standard (sn pb) n pure matte tin (pb-free) tape & reel and other options blank standard con?gurations tl tape & reel, 1 k pcs minimum, g package only lnk 354 g n - tl
LNK353/354 f 2/05 13 notes: 1. package dimensions conform to jedec specification ms-001-ab (issue b 7/85) for standard dual-in-line (dip) package with .300 inch row spacing. 2. controlling dimensions are inches. millimeter sizes are shown in parentheses. 3. dimensions shown do not include mold flash or other protrusions. mold flash or protrusions shall not exceed .006 (.15) on any side. 4. pin locations start with pin 1, and continue counter-clock- wise to pin 8 when viewed from the top. the notch and/or dimple are aids in locating pin 1. pin 6 is omitted. 5. minimum metal to metal spacing at the package body for the omitted lead location is .137 inch (3.48 mm). 6. lead width measured at package body . 7. lead spacing measured with the leads constrained to be perpendicular to plane t. .008 (.20) .015 (.38) .300 (7.62) bsc (note 7) .300 (7.62) .390 (9.91) .367 (9.32) .387 (9.83) .240 (6.10) .260 (6.60) .125 (3.18) .145 (3.68) .057 (1.45) .068 (1.73) .120 (3.05) .140 (3.56) .015 (.38) minimum .048 (1.22) .053 (1.35) .100 (2.54) bsc .014 (.36) .022 (.56) -e- pin 1 sea ting plane -d- -t - p08b dip-8b pi-2551-121504 d s .004 (.10) t e d s .010 (.25) m (note 6) .137 (3.48) minimum smd-8b pi-2546-121504 .004 (.10) .012 (.30) .036 (0.91) .044 (1.12) .004 (.10) 0 - 8 .367 (9.32) .387 (9.83) .048 (1.22) .009 (.23) .053 (1.35) .032 (.81) .037 (.94) .125 (3.18) .145 (3.68) -d- notes: 1. controlling dimensions are inches. millimeter sizes are shown in parentheses. 2. dimensions shown do not include mold flash or other protrusions. mold flash or protrusions shall not exceed .006 (.15) on any side. 3. pin locations start with pin 1, and continue counter-clock- wise to pin 8 when viewed from the top. pin 6 is omitted. 4. minimum metal to metal spacing at the package body for the omitted lead location is .137 inch (3.48 mm). 5. lead width measured at package body . 6. d and e are referenced datums on the package body . .057 (1.45) .068 (1.73) (note 5) e s .100 (2.54) (bsc) .372 (9.45) .240 (6.10) .388 (9.86) .137 (3.48) minimum .260 (6.60) .010 (.25) -e- pin 1 d s .004 (.10) g08b .420 .046 .060 .060 .046 .080 pin 1 .086 .186 .286 solder pad dimensions
LNK353/354 f 2/05 14 notes
LNK353/354 f 2/05 15 notes
LNK353/354 f 2/05 16 revision notes date d 1) released final data sheet. 10/04 e 1) added lead-free ordering information. 12/04 f 1) minor error corrections. 2/05 for the latest updates, visit our website: www.powerint.com power integrations reserves the right to make changes to its products at any time to improve reliability or manufacturability . power integrations does not assume any liability arising from the use of any device or circuit described herein. power integra tions makes no warranty herein and specifically disclaims all warranties including, without limitation, the implied warranties of merchantability, fitness for a particular purpose, and non-infringement of third party rights. patent information the products and applications illustrated herein (including transformer construction and circuits external to the products) may be covered by one or more u.s. and foreign patents, or potentially by pending u.s. and foreign patent applications assigned to power integrations. a complete list of power integrations? patents may be found at www.powerint.com. power integrations grants its customers a license under certain patent rights as set forth at http://www.powerint.com/ip.htm. life support policy power integrations? products are not authorized for use as critical components in life support devices or systems without the express written approval of the president of power integrations. as used herein: 1. a life support device or system is one which, (i) is intended for surgical implant into the body, or (ii) supports or sustains life, and (iii) whose failure to perform, when properly used in accordance with instructions for use, can be reasonably expected to result in signi?cant injury or death to the user. 2. a critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. the pi logo, topswitch , tinyswitch , linkswitch , dpa-switch , ecosmart , pi expert and pi facts are trademarks of power integrations, inc. other trademarks are property of their respective companies. ?copyright 2005, power integrations, inc. power integrations worldwide sales support locations world headquarters 5245 hellyer avenue san jose, ca 95138, usa. main: +1-408-414-9200 customer service: phone: +1-408-414-9665 fax: +1-408-414-9765 e-mail: usasales@powerint.com china (shanghai) rm 807-808a, pacheer commercial centre, 555 nanjing rd. west shanghai, p.r.c. 200041 phone: +86-21-6215-5548 fax: +86-21-6215-2468 e-mail : chinasales@powerint.com china (shenzhen) rm 2206-2207, block a, electronics science & technology bldg. 2070 shennan zhong rd. shenzhen, guangdong, china, 518031 phone: +86-755-8379-3243 fax: +86-755-8379-5828 e-mail: chinasales@powerint.com germany rueckertstrasse 3 d-80336, munich germany phone: +49-89-5527-3910 fax: +49-89-5527-3920 e-mail: eurosales@powerint.com india 261/a, ground floor 7th main, 17th cross, sadashivanagar bangalore, india 560080 phone: +91-80-5113-8020 fax: +91-80-5113-8023 e-mail: indiasales@powerint.com italy via vittorio veneto 12 20091 bresso mi italy phone: +39-028-928-6000 fax: + 39-028-928-6009 e-mail: eurosales@powerint.com japan keihin tatemono 1st bldg 2-12-20 shin-yokohama, kohoku-ku, yokohama-shi, kanagawa ken, japan 222-0033 phone: +81-45-471-1021 fax: +81-45-471-3717 e-mail: japansales@powerint.com korea rm 602, 6fl korea city air terminal b/d, 159-6 samsung-dong, kangnam-gu, seoul, 135-728, korea phone: +82-2-2016-6610 fax: +82-2-2016-6630 e-mail: koreasales@powerint.com singapore 51 newton road, #15-08/10 goldhill plaza, singapore, 308900 phone: +65-6358-2160 fax: +65-6358-2015 e-mail: singaporesales@powerint.com taiwan 5f, no. 318, nei hu rd., sec. 1 nei hu dist. taipei, taiwan 114, r.o.c. phone: +886-2-2659-4570 fax: +886-2-2659-4550 e-mail: taiwansales@powerint.com europe hq 1st floor, st. james?s house east street, farnham surrey, gu9 7tj united kingdom phone: +44 (0) 1252-730-140 fax: +44 (0) 1252-727-689 e-mail: eurosales@powerint.com applications hotline world wide +1-408-414-9660 applications fax world wide +1-408-414-9760

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